Verilink AS2000: The Basics (880-502981-001) Product Manual Instrukcja Użytkownika Pobierz pdf (Strona 157)

Acronyms and Definitions

Verilink Access System 2000: Basics Glossary-37

packet A group of fixed-length bits,

including overhead control bits,

transmitted through an X.25

network as a whole.

path code violation See

code violation—path (CV-P)

payload loopback (PLB) This loopback loops the signal

from the network back towards the

network. The signal passes

through the CSU when using PLB,

including the repeater, making it

useful for testing the CSU from the

far-end circuit.

P-bits P-bits contain parity information.

There are two P-bits per DS3

frame, located in the first bit

position in block 1 of subframe 3

and subframe 4. They provide a

means for in-service error

detection.

PCV P-bit Coding Violation. A DS3

circuit P-bit Parity error event,

counted when the received P-bit

code on the DS3 M-frame is not

identical to the corresponding

locally-calculated code.

performance data Information generated and stored

by the CSU that indicates the

quality of a signal received from

the equipment or network. The

performance data is stored in

registers for operator retrieval.

performance monitoring The configuration options that

allow you to examine performance

statistics which can be gathered

and reported during specified

intervals.

Permanent Virtual Circuit (PVC) In frame relay networks, a logical

link between endpoints defined by

network management. It consists

of a network element address and

data link connection identifier for

both the originating and

terminating end points.

PES P-bit Errored Second. A second

during which a DS3 circuit has one

or more

PCV

s OR one or more

out-of-frame (OOF)

defects OR a

detected incoming

AIS

. The PES

count is not increased when

UAS

are counted.

phase The time or angle that a data

signal is delayed with respect to a

reference point(s).

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